1. Field of the Invention
The present invention relates to a method for forming a low temperature polysilicon complementary metal oxide semiconductor thin film transistor (LTPS CMOS TFT), and more particularly, to a method that utilizes six photo-etching processes to form an LTPS CMOS TFT.
2. Description of the Prior Art
A liquid crystal display is broadly applied to portable electronic apparatuses, such as notebooks and personal digital assistants (PDAs), because of its thin display panel, low power consumption, and low-radiation. As the requirements of high quality displays increase, flat panels with high quality and low price are demanding in the future. LTPS TFT is one of the important technologies for achieving the goal.
An LTPS TFT-LCD includes at least a transparent substrate, a pixel array region, a scan line driving circuit region, and a data line driving circuit region. The pixel array region comprises a plurality of parallel scan lines, a plurality of parallel data lines, and a liquid crystal molecule layer. Each scan line and each data line define a pixel, and each pixel further comprises a TFT and a storage capacitor. Current LTPS TFT-LCD integrates a standard driving IC in a liquid crystal panel by utilizing LTPS CMOS TFT processes, thus the size of displays and the cost can be reduced.
FIGS. 1-9 are schematic diagrams demonstrating a method for forming a top gate LPTS CMOS TFT 56 according to the prior art. As shown in FIG. 1, the LTPS CMOS TFT 56 of the prior art is manufactured on a glass substrate 10, and the glass substrate 10 surface comprises a first region I and a second region II for respectively forming an N type metal oxide semiconductor thin film transistor 52 (NMOS TFT) and a P type metal oxide semiconductor thin film transistor 54 (PMOS TFT) of a driving IC. The glass substrate 10 surface further comprises a pixel array region (not shown in FIG. 1) for forming a plurality of NMOS TFTs arranged in an array to control image display of each pixel.
According to the prior art, an undoped polysilicon layer (not shown in FIG. 1) is first formed on the glass substrate 10, and a first photo-etching process is performed to form a patterned undoped polysilicon layer 12 on both the first region I and the second region II of the glass substrate 10. As shown in FIG. 2, a low temperature deposition process or a thermal oxidization process is performed to form a gate insulating layer 14 on the glass substrate 10 that covers the patterned undoped polysilicon layer 12. Then a photo resist layer (not shown in FIG. 2) is formed on the gate insulating layer 14, and a second photo-etching process is performed to form a patterned photo resist layer 16 in the photo resist layer. Then, a implantation process 18 is performed to implant phosphor ions into the patterned undoped polysilicon layer 12 that is not covered by the patterned photo resist layer 16, such that two N type heavily doped areas 20s and 20d being a source and a drain of the NMOS TFT 52 respectively are formed. Finally the patterned photo resist layer 16 is removed.
As shown in FIG. 3, another photo resist layer (not shown in FIG. 3) is formed on the glass substrate 10, and a third photo-etching process is performed to form a patterned photo resist layer 22 in the photo resist layer. Then an implantation process 24 is performed to implant phosphor ions into the patterned undoped polysilicon layer 12 that is not covered by the patterned photo resist layer to form two N type lightly doped drain (LDD) areas.
As shown in FIG. 4, another photo resist layer (not shown in FIG. 4) is formed on the glass substrate 10 after removing the patterned photo resist layer 22, and a fourth photo-etching process is performed to form a patterned photo resist layer 28. Then an implantation process 30 is performed to implant phosphor ions into the patterned undoped polysilicon layer 12 that is not covered by the patterned photo resist layer 28, such that two P type heavily doped areas 32s and 32d being a source and a drain of the PMOS TFT 54 respectively are formed. The patterned undoped polysilicon layer 12 is used as a channel. Finally the patterned photo resist layer 28 is removed.
As shown in FIGS. 5-7, an aluminum layer (not shown) is formed on the gate insulating layer 14. Then a fifth photo-etching process is performed to form two gate electrodes 34 and 36 on the surface of the gate insulating layer 14, and a interlayer dielectric (ILD) 38, which covers the gate electrodes 34 and 36, is formed on the glass substrate 10. Afterward, a sixth photo-etching process is performed to form a plurality of via holes 40, which reach the sources 20s and 32s, and the drains 20d and 32d respectively, in the interlayer dielectric 38. Following that, a conductive layer (not shown) is formed and filled into the via holes 40. Finally a seventh photo-etching process is performed to remove parts of the conductive layer, such that a source 42s and a drain 42d of the NMOS TFT 52 and a source 44s and a drain 44d of the PMOS TFT 54 are formed.
As shown in FIGS. 8 and 9, a passivation layer 46 is performed on the glass substrate 10, and a eighth photo-etching process is performed to form a plurality of contact holes 48, which reach the sources 42s and 44s, and the drains 42d and 44d, in the passivation layer 46. Finally a transparent conductive layer 50 is performed on the glass substrate 10, and a ninth photo-etching process is performed to remove parts of the transparent conductive layer 50, such that the NMOS TFT 52 and the PMOS TFT 54 are formed.
According to the method for forming the LTPS CMOS TFT of the prior art, nine photo-etching processes are performed to respectively define the patterned polysilicon layer, the source and drain of the NMOS TFT, the LDD of the NMOS TFT, the source, drain, and gate of the PMOS TFT, the via holes, source, and drain of the interlayer dielectric, the contact holes of the passivation layer, and the pattern of the transparent conductive layer. Therefore, the entire process is complex and takes a lot of time. Furthermore, the alignment deviation occurs easily because of excessive photo-etching processes.